1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory such as EPROM (Erasable and Programmable Read-Only Memory).
2. Description of the Related Art
Japanese Patent Application Laid-Open (JP-A) No. 2005-50423 discloses a technique for suppressing read access delay due to a parasitic capacitance between the bit lines of EPROM. This EPROM includes an actual cell amplifier, a reference amplifier and a sense amplifier for comparing output levels of the actual cell amplifier and the reference amplifier with each other and outputting a read signal. The actual cell amplifier amplifies the potential of the bit line of which the level changes in accordance with on/off state of a memory cell selected for reading. The reference amplifier amplifies the potential of the bit line connected with a reference cell which is set to a comparative conduction state. A transistor in forward direction diode connection is connected between the bit line at the input side (end) of the actual cell amplifier and a grounding potential, and another transistor in forward direction diode connection is connected between the bit line at the input side of the reference amplifier and the grounding potential.
In this EPROM, when a memory cell in off state with data 0 written therein is read, the drain of this memory cell is connected to the grounding potential by the transistor driven by a select signal. Since the memory cell is in off state, no current flows in the memory cell. However, due to the parasitic capacitance between the bit line connected with the source of the memory cell and the bit line connected with the drain of the memory cell, the potential of the bit line connected with the source of the memory cell (i.e., the bit line connected to the input side of the actual cell amplifier) is pulled by the grounding potential, and therefore, a charge current flows to the bit line from the input side of the actual cell amplifier. On the other hand, the input side of the actual cell amplifier is connected to the grounding potential by the transistor in forward diode connection, and therefore, DC current flows to the grounding potential through this transistor. As a result, the charge start timing of the parasitic capacitance is made short and read delay time of reading is reduced.
The EPROM described above, however, is a circuit for increasing initial charge speed from the sense amplifier, and fails to take into consideration the initial potential of the selected bit line which is changed according to the operating condition. Therefore, a sufficient effect may not be obtained for all the read operations.